Digital Logic Design MCQ (Multiple Choice Questions)

1. What is the simplified Boolean expression for Y = A + A’B?

a) AB

b) A’B

c) A’ + B

d) A + B

Explanation: Using the absorption law: A + A’B = A(1 + B) + A’B – wait, more directly A + A’B = A + B (since when A=1 the term is 1 regardless of B, and when A=0 the second term gives B).

2. What is the octal form of the hexadecimal number F3B1?

a) 178543

b) 172101

c) 171661

d) 171541

Explanation: F3B1₁₆ = 1111 0011 1011 0001₂ → grouping 3 bits from right: 1 111 001 110 110 001₈ = 171661₈.

3. In 16-bit 2’s complement representation, what is the binary for –28?

a) 1000 0000 1110 0100

b) 0000 0000 1110 0100

c) 1111 1111 1110 0100

d) 1111 1111 0001 1100

Explanation: +28 = 0000 0000 0001 1100 → 1’s complement = 1111 1111 1110 0011 → 2’s complement = add 1 → 1111 1111 1110 0100.

4. For 8-bit 2’s complement numbers A=1111 1010 and B=0000 1010, what is their product in 2’s complement (8-bit result)?

a) 1100 0100

b) 1001 1100

c) 1010 0101

d) 1101 0101

Explanation: 11111010₂ = –6, 00001010₂ = 10 → product = –60. 60 = 00111100₂ → 2’s complement = 11000100₂.

5. What is the minimum number of 2-input NOR gates required to implement f = C + AB?

a) 2

b) 3

c) 4

d) 5

Explanation: f = C + AB = (C’ · (A’ + B’))’ → three NOR gates: (A NOR B) → A’ + B’, then NOR with C’ gives the final output.

6. How many 2-input NAND gates are needed to implement W = AB + CD + EF?

a) 6

b) 7

c) 8

d) 9

Explanation: Three NANDs produce AB, CD, EF (with inverters if needed), then three more NANDs implement the OR function using De Morgan: (AB + CD + EF) = ((AB)’ · (CD)’ · (EF)’)’.

7. Simplify the function f(a,b,c) = Σm(0,2,5,7) using K-map.

a) a’c’

b) a’c’ + a’c

c) a’c’ + ac’

d) a’c’ + ac

Explanation: K-map groups: 0 & 2 → a’c’, 5 & 7 → ac → f = a’c’ + ac.

8. Convert (312)₈ to decimal.

a) 201

b) 202

c) 203

d) 204

Explanation: 3×64 + 1×8 + 2×1 = 192 + 8 + 2 = 202.

9. In toggle mode, a JK flip-flop has:

a) J=0, K=1

b) J=1, K=1

c) J=0, K=0

d) J=1, K=0

Explanation: J = K = 1 causes the flip-flop to complement its previous state on each clock edge (toggle).

10. Find the base R where (141)ᵣ = 997₁₀.

a) 3

b) 4

c) 5

d) 6

Explanation: 1·R² + 4·R + 1 = 997 → R² + 4R – 996 = 0. However, standard MCQ variant solves for 61 (common typo): R=6 gives 36+24+1=61. Assuming the common version → R=6.

11. De-Morgan’s theorem states that:

a) (A+B)’ = A’ · B

b) (A·B)’ = A’ + B’

c) (A·B)’ = A’ + B

d) (A+B)’ = A + B

Explanation: Second De Morgan law: complement of product = sum of complements.

12. The hexadecimal number (1E.43)₁₆ is equivalent to which octal number?

a) (36.506)₈

b) (36.206)₈

c) (35.506)₈

d) (35.206)₈

Explanation: 1E.43₁₆ → binary 0001 1110 . 0100 0011 → octal 36.206₈.

13. For a counter with sequence 0,2,3,1,0 using D flip-flops, what are the D inputs?

a) D₁ = Q₀’, D₀ = Q₁’

b) D₁ = Q₀, D₀ = Q₁

c) D₁ = Q₀, D₀ = Q₁’

d) D₁ = Q₀’, D₀ = Q₁

Explanation: State transitions → D₁ = ~Q₀, D₀ = Q₁ (from excitation table + K-map).

14. For a 2-bit MUX to output XOR of C and D, what are the data inputs A₀, A₁, A₂, A₃?

a) 0,1,1,0

b) 0,0,1,0

c) 0,1,0,0

d) 1,1,1,0

Explanation: C XOR D = ~C·D + C·~D → select 00→0, 01→1, 10→1, 11→0.

15. Which input sequence for cross-coupled RS latch with NOR gates may cause oscillation?

a) 11, 00

b) 01, 10

c) 10, 01

d) 00, 11

Explanation: Applying 00 then 11 can cause a race condition → metastable / oscillation.

16. If S and R are both 0 in SR latch with NOR gates, the output is:

a) Q=0, Q’=1

b) Q=1, Q’=0

c) Q=1, Q’=1

d) Indeterminate

Explanation: When S=R=0 the outputs become Q=1, Q’=1 (forbidden/invalid state in NOR SR latch).

17. For a traffic light FSM with green 70s, yellow 5s, red 75s, clock 5s period, minimum flip-flops needed?

a) 5

b) 4

c) 6

d) 7

Explanation: Total 150 s / 5 s = 30 states → 2⁵ = 32 > 30 → minimum 5 flip-flops.

18. The sequence at Q_A in the given circuit (assuming initial reset) is:

a) 0010111…

b) 0001011…

c) 0101111…

d) 0110100…

Explanation: Typical Johnson/modified counter feedback pattern yields repeating 0110100…

19. If a DAC has full-scale output 20 mA and resolution 80 µA, the percentage resolution is:

a) 0.8

b) 0.07

c) 3.9

d) 0.4

Explanation: Resolution % = (step / full-scale) × 100 = (80 µA / 20 mA) × 100 = 0.4%.

20. If DAC resolution is 0.4% of full-scale, it is approximately a:

a) 16-bit

b) 10-bit

c) 8-bit

d) 12-bit

Explanation: 100 / 2ⁿ ≈ 0.4 → 2ⁿ ≈ 250 → n ≈ 8 bits.

21. Which is not a standard type of NAND Flash Memory?

a) SLC

b) QLC

c) MLC

d) CLC

Explanation: CLC (eight-level cell) is not a standard commercial NAND type.

22. The octal equivalent of decimal 65 is:

a) 111

b) 101

c) 100

d) 110

Explanation: 65 ÷ 8 = 8 r1 → 8 ÷ 8 = 1 r0 → 1 ÷ 8 = 0 r1 → 101₈.

23. The sum of binary 101 and 1101 is:

a) 10110

b) 10010

c) 10101

d) 10100

Explanation: 00101 + 01101 = 10010 (5 + 13 = 18).

24. The main purpose of a Karnaugh map in Boolean algebra is:

a) Convert to truth table

b) Verify equation

c) Identify variables

d) Simplify expressions

Explanation: K-maps allow visual grouping of 1s to obtain minimal sum-of-products / product-of-sums.

25. Convert hexadecimal C6 to binary.

a) 10010110

b) 11000100

c) 11000110

d) 10100110

Explanation: C = 1100, 6 = 0110 → 11000110₂.

26. Binary 101110110 equals decimal:

a) 468

b) 412

c) 374

d) 326

Explanation: 256 + 64 + 32 + 16 + 4 + 2 = 374.

27. How many different numbers can be represented with 4 bits?

a) 16

b) 8

c) 12

d) 4

Explanation: 2⁴ = 16 possible combinations (0 to 15).

28. One megabyte in binary terms is:

a) 10³ bytes

b) 10⁴ bytes

c) 2¹⁰ bytes

d) 2²⁰ bytes

Explanation: 1 MB = 1024 KB = 1024 × 1024 bytes = 2²⁰ bytes.

29. Binary 110110101 equals decimal:

a) 333

b) 437

c) 349

d) 477

Explanation: 256+128+32+16+4+1 = 437.

30. Boolean algebra obeys which properties?

a) Commutative only

b) Distributive only

c) Associative only

d) All three

Explanation: Commutative, associative, and distributive laws all hold.

31. Sum of binary 1101111 and 1100101 is:

a) 100011100

b) 100000110

c) 11110000

d) 11010100

Explanation: 1101111 + 1100101 = 11010100 (with carries).

32. 8-bit 2’s complement representation of –14 is:

a) 11110010

b) 00001110

c) 10001110

d) 01110001

Explanation: 14 = 00001110 → invert = 11110001 → +1 = 11110010.

33. Octal equivalent of binary 1011101011 is:

a) 7353

b) 1353

c) 5651

d) 5657

Explanation: 001 011 101 011 → 1 3 5 3₈.

34. Number of 1s in binary representation of 3×4096 + 15×256 + 5×16 + 3:

a) 8

b) 9

c) 10

d) 12

Explanation: 12288 + 3840 + 80 + 3 = 16211₁₀ → binary has ten 1s.

35. Latches using NOR/NAND remain latched due to:

a) Low voltages

b) Synchronous operation

c) Gate impedance

d) Cross coupling

Explanation: Output of one gate feeds back to input of the other → regenerative feedback.

36. An S-R flip-flop can be used as a:

a) Pulse generator

b) Race detector

c) Switch debouncer

d) Oscillator

Explanation: It ignores rapid contact bounces and latches the stable state.

37. How many valid entries exist in the truth table of a basic SR flip-flop?

a) 1

b) 2

c) 3

d) 4

Explanation: Set (S=1,R=0), Reset (S=0,R=1), Hold (S=0,R=0); S=R=1 is invalid.

38. When both J and K inputs of a JK flip-flop cycle through all combinations and return, the output:

a) Becomes invalid

b) Always changes

c) Remains unchanged

d) Always toggles

Explanation: Full cycle of inputs returns flip-flop to original state (symmetric behavior).

39. In a gated D flip-flop the characteristic is:

a) Q follows D when enabled

b) Q toggles when D=1

c) Only one input can be high

d) Complement of D is stored

Explanation: When gate (enable) is active, Q ← D; otherwise holds.

40. A basic SR flip-flop is constructed by cross-coupling:

a) AND/OR gates

b) XOR/XNOR gates

c) NOR or NAND gates

d) AND/NOR gates

Explanation: Two NOR or two NAND gates with cross-coupled feedback form SR latch.

41. Circuits whose output depends on present input and past outputs are called:

a) Combinational

b) Sequential

c) Latches only

d) Flip-flops only

Explanation: Sequential circuits possess memory (feedback or storage elements).

42. Which type of logic circuit generally has faster operation?

a) Combinational

b) Sequential

c) Latches

d) Flip-flops

Explanation: No memory → no clock delay → faster propagation.

43. How many main categories of sequential circuits exist?

a) 2

b) 3

c) 4

d) 5

Explanation: Synchronous and asynchronous sequential circuits.

44. The basic memory element in sequential circuits is often called:

a) Flip-flop

b) Latch

c) Strobe

d) Adder

Explanation: Latch is the fundamental level-sensitive storage element.

45. A basic latch can be formed using:

a) Two inverters connected back-to-back

b) Two comparators

c) Two amplifiers

d) Two adders

Explanation: Two inverters in a loop create a bistable element (SR latch variant).

46. In an SR flip-flop, Q = 0 typically means the flip-flop is:

a) Set

b) Reset

c) Holding previous state

d) In toggle mode

Explanation: Reset state → Q = 0, Q’ = 1.

47. The outputs of a latch remain unchanged until:

a) A trigger pulse changes the state

b) Any random pulse arrives

c) No more clock pulses arrive

d) Edge-trigger occurs

Explanation: Level-sensitive latches hold until enable/input condition changes.

48. A trigger pulse in sequential circuits is primarily used to:

a) Initiate / start an operation cycle

b) Reverse the entire cycle

c) Prevent any cycle

d) Enhance cycle speed

Explanation: It enables or clocks the state change.

49. NOR-based SR latch is considered asynchronous because:

a) It uses inverted outputs

b) It requires triggering

c) It uses cross-coupled feedback

d) It is both inverted and triggered

Explanation: No clock → state changes immediately when inputs change.

50. A counter is a sequential circuit that primarily stores / counts:

a) Only output values

b) Number of occurrences of an event

c) Only clock rising/falling edges

d) Only input values

Explanation: Counters tally pulses/events (usually clock edges).